1. Field of the Invention
The present invention relates to a single chip processor, and more particularly, to an improvement of a test function of the single chip processor.
2. Description of the Related Art
In a single chip processor, in order to realize a high speed operation, Harvard architecture has been adopted to isolate a data path for instruction codes from a data path for operational data. Particularly in a digital signal processor, an external instruction read-only memory (ROM) or an external instruction random access memory (RAM) is not preferable in view of the access speed and the number of external pins. Therefore, an instruction ROM (or RAM) is incorporated into the single chip processor. In addition, a test program for testing internal circuits has to be incorporated into the instruction memory. As a result, a user processing program area in the instruction memory is reduced in size.
Particularly, since one instruction is formed by a plurality of control fields; in a digital signal processor (DSP) having horizontal type instruction codes, the instructions are very complex. Therefore, it is actually impossible to store all the test programs in the instruction memory. In addition, it is impossible to verify other events which are not included in the test program stored in the instruction memory. Further, it is difficult to verify the operation of the internal circuits after shipping.
In another prior art single chip processor (See JP-A-2-12436), a test program is written into a RAM and a testing operation is, in turn, carried out in accordance with the test program stored in the RAM. In this processor, however, two read operations are carried out for every instruction cycle, thus the test speed is very low. Note that only one read operation is carried out for an instruction cycle of the processor.